pi74fct16841t/162841t 20-bit transparent latch 1 ps2078a 01/15/95 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct16841t pi74fct162841t fast cmos 20-bit transparent latch logic block diagram product description pericom semiconductor?s pi74fct series of logic circuits are pro- duced in the company?s advanced 0.8 micron cmos technology, achieving industry leading speed grades. the pi74fct16841t and pi74fct162841t are 20-bit wide transparent latches designed to provide temporary storage of data and can be used as i/o ports, memory address latches, and bus drivers. the output enable and latch enable controls allow the devices to be operated as two 10-bit latches or one 20-bit latch. signal pins are arranged in a flow-through organization for ease of layout and hysteresis is designed into all inputs to improve noise margin. the output buffers on the pi74fct16841t and pi74fct162841t are especially designed for driving high-capacitance loads and low impedance backplanes and include a power-off disable function allowing ?live insertion? of boards when the devices are used as backplane drivers. the pi74fct162841t has 24 ma balanced output drivers. it is designed with current limiting resistors at its outputs to control the output edge rate resulting in lower ground bounce and undershoot. this eliminates the need for external terminating resistors for most interface applications. product features common features ? pi74fct16841t and pi74fct162841t are high-speed, low power devices with high current drive ?v cc = 5v 10% ? hysteresis on all inputs ? packages available: ? 56-pin 240 mil wide plastic tssop (a) ? 56-pin 300 mil wide plastic ssop (v) pi74fct16841t features ? high output drive: i oh = ?32 ma; i ol = 64 ma ? power off disable outputs permit ?live insertion? ? typical v olp (output ground bounce) < 1.0v at v cc = 5v, t a = 25c pi74fct162841t features ? balanced output drivers: 24 ma ? reduced system switching noise ? typical v olp (output ground bounce) < 0.6v at v cc = 5v, t a = 25c d 1 oe c 1 le 1 d 1 1 q 1 to 9 other channels d 2 oe c 2 le 2 d 1 2 q 1 to 9 other channels
pi74fct16841t/162841t 20-bit transparent latch 2 ps2078a 01/15/95 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pin name description xdx data inputs xle latch enable input (active low) xoe output enable input (active low) xqx 3-state outputs product pin description product configuration inputs outputs xdx xle xoe xqx hhl h lhl l xll q (2) xxh z truth table (1) 1. h = high voltage level l = low voltage level x = don?t care z = high impedance 2. output level before xle high-to-low transition. 1 oe 1 1 q 1 2 1 q 2 3 gnd 4 1 q 3 5 1 q 4 6 v cc 7 1 q 5 8 1 q 6 9 1 q 7 10 gnd 11 1 q 8 12 1 q 9 13 1 q 10 14 2 q 1 15 2 q 2 16 2 q 3 17 gnd 18 2 q 4 19 2 q 5 20 2 q 6 21 v cc 22 2 q 7 23 2 q 8 24 1 le 56 1 d 1 55 1 d 2 54 gnd 53 1 d 3 52 1 d 4 51 v cc 50 1 d 5 49 1 d 6 48 1 d 7 47 gnd 46 1 d 8 45 1 d 9 44 1 d 10 43 2 d 1 42 2 d 2 41 2 d 3 40 gnd 39 2 d 4 38 2 d 5 37 2 d 6 36 v cc 35 2 d 7 34 2 d 8 33 gnd 25 2 q 9 26 2 q 10 27 2 oe 28 gnd 32 2 d 9 31 2 d 10 30 2 le 29 56-pin v56 a56
pi74fct16841t/162841t 20-bit transparent latch 3 ps2078a 01/15/95 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dc electrical characteristics (over the operating range, t a = ?40c to +85c, v cc = 5.0v 10%) parameters description test conditions (1) min. typ (2) max. units v ih input high voltage guaranteed logic high level 2.0 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current v cc = max. v in = v cc 1a i il input low current v cc = max. v in = gnd ?1 a i ozh high impedance v cc = max. v out = 2.7v 1 a i ozl output current v cc = max. v out = 0.5v ?1 a v ik clamp diode voltage v cc = min., i in = ?18 ma ?0.7 ?1.2 v i os short circuit current v cc = max. (3) , v out = gnd ?80 ?140 ?200 ma i o output drive current v cc = max. (3) , v out = 2.5v ?50 ?180 ma v h input hysteresis 100 mv pi74fct16841t output drive characteristics (over the operating range) parameters description test conditions (1) min. typ (2) max. units v oh output high voltage v cc = min., v in = v ih or v il i oh = ?3.0 ma 2.5 3.5 v i oh = ?15.0 ma 2.4 3.5 i oh = ?32.0 ma 2.0 3.0 v ol output low voltage v cc = min., v in = v ih or v il i ol = 64 ma 0.2 0.55 v i off power down disable v cc = 0v, v in or v out 4.5v ? ? 100 a pi74fct162841t output drive characteristics (over the operating range) parameters description test conditions (1) min. typ (2) max. units v oh output high voltage v cc = min., v in = v ih or v il i oh = ?24.0 ma 2.4 3.3 v v ol output low voltage v cc = min., v in = v ih or v il i ol = 24 ma 0.3 0.55 v i odl output low current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) 60 115 150 ma i odh output high current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) ?60 ?115 ?150 ma notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is determined by device characterization but is not production tested. capacitance (t a = 25c, f = 1 mhz) parameters (4) description test conditions typ max. units c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature ................................................................... ?65c to +150c ambient temperature with power applied .................................... ?40c to +85c supply voltage to ground potential (inputs & vcc only) .............. ?0.5v to +7.0v supply voltage to ground potential (outputs & d/o only) ........... ?0.5v to +7.0v dc input voltage ............................................................................ ?0.5v to +7.0v dc output current ..................................................................................... 120 ma power dissipation .......................................................................................... 1.0w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
pi74fct16841t/162841t 20-bit transparent latch 4 ps2078a 01/15/95 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device. 2. typical values are at vcc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at vcc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the icc formula. these limits are guaranteed but not tested. 6. i c =i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp /2 + fi n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz. power supply characteristics parameters description test conditions (1) min. typ (2) max. units i cc quiescent power v cc = max. v in = gnd 0.1 500 a supply current or v cc d i cc supply current per v cc = max. v in = 3.4v (3) 0.5 2.5 ma input @ ttl high i ccd supply current per v cc = max., v in = v cc 0.15 0.25 ma/ input per mhz (4) outputs open v in = gnd mhz oe = gnd; le = vcc one input toggling 50% duty cycle i c total power supply v cc = max., v in = v cc 1.7 4.0 (5) ma current (6) outputs open v in = gnd f cp = 10 mh z 50% duty cycle v in = 3.4v 2.0 5.0 (5) oe = gnd; le = vcc v in = gnd f i = 5 mh z one bit toggling v cc = max., v in = v cc 3.2 6.5 (5) outputs open v in = gnd f cp = 10 mh z 50% duty cycle v in = 3.4v 5.2 14.5 (5) oe = gnd; le = vcc v in = gnd eight bits toggling f i = 2.5 mh z 50% duty cycle
pi74fct16841t/162841t 20-bit transparent latch 5 ps2078a 01/15/95 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pi74fct16841 switching characteristics over operating range 16841at 16841bt 16841ct 16841dt 16841et com. com. com. com. com. parameters description conditions (1) min max min max min max min max min max unit t plh propagation delay c l = 50 pf 1.5 9.0 1.5 6.5 1.5 5.5 1.5 4.2 1.5 3.4 ns t phl x d x to x q x r l = 500 w (le = high) c l = 300 pf (3) 1.5 13.0 1.5 13.0 1.5 13.0 1.5 13.0 1.5 7.5 ns r l = 500 w t plh propagation delay c l = 50 pf 1.5 12.0 1.5 8.0 1.5 6.4 1.5 4.0 1.5 3.7 ns t phl x le to x q x r l = 500 w c l = 300 pf (3) 1.5 16.0 1.5 15.5 1.5 15.0 1.5 8.0 1.5 7.5 ns r l = 500 w t pzh output enable time c l = 50 pf 1.5 11.5 1.5 8.0 1.5 6.5 1.5 4.8 1.5 4.4 ns t pzl x oe to x q x r l = 500 w c l = 300 pf (4) 1.5 23.0 1.5 14.0 1.5 12.0 1.5 9.0 1.5 9.0 ns r l = 500 w t phz output disable time (3) c l = 5 pf (3) 1.5 7.0 1.5 6.0 1.5 5.7 1.5 4.0 1.5 4.0 ns t plz x oe to x q x r l = 500 w c l = 50 pf 1.5 8.0 1.5 7.0 1.5 6.0 1.5 5.4 1.5 4.0 ns r l = 500 w t su setup time high or c l = 50 pf 2.5 ? 2.5 ? 2.5 ? 1.0 ? 1.0 ? ns low, x d x to x le r l = 500 w t h hold time high or 2.5 ? 2.5 ? 2.5 ? 1.0 ? 1.0 ? ns low, x d x to x le t w xle pulse width high (3) 4.0 ? 4.0 ? 4.0 ? 4.0 ? 3.0 ? ns t sk ( o ) output skew (4) ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ns notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not production tested. 4. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design.
pi74fct16841t/162841t 20-bit transparent latch 6 ps2078a 01/15/95 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct16841 switching characteristics over operating range 162841at 162841bt 162841ct 162841dt 162841et com. com. com. com. com. parameters description conditions (1) min max min max min max min max min max unit t plh propagation delay c l = 50 pf 1.5 9.0 1.5 6.5 1.5 5.5 1.5 4.2 1.5 3.4 ns t phl x d x to x q x r l = 500 w (le = high) c l = 300 pf (3) 1.5 13.0 1.5 13.0 1.5 13.0 1.5 13.0 1.5 7.5 ns r l = 500 w t plh propagation delay c l = 50 pf 1.5 12.0 1.5 8.0 1.5 6.4 1.5 4.0 1.5 3.7 ns t phl x le to x q x r l = 500 w c l = 300 pf (3) 1.5 16.0 1.5 15.5 1.5 15.0 1.5 8.0 1.5 7.5 ns r l = 500 w t pzh output enable time c l = 50 pf 1.5 11.5 1.5 8.0 1.5 6.5 1.5 4.8 1.5 4.4 ns t pzl x oe to x q x r l = 500 w c l = 300 pf (4) 1.5 23.0 1.5 14.0 1.5 12.0 1.5 9.0 1.5 9.0 ns r l = 500 w t phz output disable time (3) c l = 5 pf (3) 1.5 7.0 1.5 6.0 1.5 5.7 1.5 4.0 1.5 4.0 ns t plz x oe to x q x r l = 500 w c l = 50 pf 1.5 8.0 1.5 7.0 1.5 6.0 1.5 5.4 1.5 4.0 ns r l = 500 w t su setup time high or c l = 50 pf 2.5 ? 2.5 ? 2.5 ? 1.0 ? 1.0 ? ns low, x d x to x le r l = 500 w t h hold time high or 2.5 ? 2.5 ? 2.5 ? 1.0 ? 1.0 ? ns low, x d x to x le t w xle pulse width high (3) 4.0 ? 4.0 ? 4.0 ? 4.0 ? 3.0 ? ns t sk ( o ) output skew (4) ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ns notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not production tested. 4. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design.
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